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* Add a storage layer for attachments * Fix some bug * fix test * Fix copyright head and lint * Fix bug * Add setting for minio and flags for migrate-storage * Add documents * fix lint * Add test for minio store type on attachments * fix test * fix test * Apply suggestions from code review Co-authored-by: guillep2k <18600385+guillep2k@users.noreply.github.com> * Add warning when storage migrated successfully * Fix drone * fix test * rebase * Fix test * display the error on console * Move minio test to amd64 since minio docker don't support arm64 * refactor the codes * add trace * Fix test * remove log on xorm * Fi download bug * Add a storage layer for attachments * Add setting for minio and flags for migrate-storage * fix lint * Add test for minio store type on attachments * Apply suggestions from code review Co-authored-by: guillep2k <18600385+guillep2k@users.noreply.github.com> * Fix drone * fix test * Fix test * display the error on console * Move minio test to amd64 since minio docker don't support arm64 * refactor the codes * add trace * Fix test * Add URL function to serve attachments directly from S3/Minio * Add ability to enable/disable redirection in attachment configuration * Fix typo * Add a storage layer for attachments * Add setting for minio and flags for migrate-storage * fix lint * Add test for minio store type on attachments * Apply suggestions from code review Co-authored-by: guillep2k <18600385+guillep2k@users.noreply.github.com> * Fix drone * fix test * Fix test * display the error on console * Move minio test to amd64 since minio docker don't support arm64 * don't change unrelated files * Fix lint * Fix build * update go.mod and go.sum * Use github.com/minio/minio-go/v6 * Remove unused function * Upgrade minio to v7 and some other improvements * fix lint * Fix go mod Co-authored-by: guillep2k <18600385+guillep2k@users.noreply.github.com> Co-authored-by: Tyler <tystuyfzand@gmail.com>
191 lines
6.8 KiB
Markdown
Vendored
191 lines
6.8 KiB
Markdown
Vendored
# cpuid
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Package cpuid provides information about the CPU running the current program.
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CPU features are detected on startup, and kept for fast access through the life of the application.
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Currently x86 / x64 (AMD64/i386) and ARM (ARM64) is supported, and no external C (cgo) code is used, which should make the library very easy to use.
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You can access the CPU information by accessing the shared CPU variable of the cpuid library.
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Package home: https://github.com/klauspost/cpuid
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[![GoDoc][1]][2] [![Build Status][3]][4]
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[1]: https://godoc.org/github.com/klauspost/cpuid?status.svg
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[2]: https://godoc.org/github.com/klauspost/cpuid
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[3]: https://travis-ci.org/klauspost/cpuid.svg?branch=master
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[4]: https://travis-ci.org/klauspost/cpuid
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# features
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## x86 CPU Instructions
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* **CMOV** (i686 CMOV)
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* **NX** (NX (No-Execute) bit)
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* **AMD3DNOW** (AMD 3DNOW)
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* **AMD3DNOWEXT** (AMD 3DNowExt)
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* **MMX** (standard MMX)
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* **MMXEXT** (SSE integer functions or AMD MMX ext)
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* **SSE** (SSE functions)
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* **SSE2** (P4 SSE functions)
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* **SSE3** (Prescott SSE3 functions)
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* **SSSE3** (Conroe SSSE3 functions)
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* **SSE4** (Penryn SSE4.1 functions)
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* **SSE4A** (AMD Barcelona microarchitecture SSE4a instructions)
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* **SSE42** (Nehalem SSE4.2 functions)
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* **AVX** (AVX functions)
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* **AVX2** (AVX2 functions)
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* **FMA3** (Intel FMA 3)
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* **FMA4** (Bulldozer FMA4 functions)
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* **XOP** (Bulldozer XOP functions)
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* **F16C** (Half-precision floating-point conversion)
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* **BMI1** (Bit Manipulation Instruction Set 1)
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* **BMI2** (Bit Manipulation Instruction Set 2)
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* **TBM** (AMD Trailing Bit Manipulation)
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* **LZCNT** (LZCNT instruction)
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* **POPCNT** (POPCNT instruction)
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* **AESNI** (Advanced Encryption Standard New Instructions)
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* **CLMUL** (Carry-less Multiplication)
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* **HTT** (Hyperthreading (enabled))
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* **HLE** (Hardware Lock Elision)
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* **RTM** (Restricted Transactional Memory)
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* **RDRAND** (RDRAND instruction is available)
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* **RDSEED** (RDSEED instruction is available)
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* **ADX** (Intel ADX (Multi-Precision Add-Carry Instruction Extensions))
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* **SHA** (Intel SHA Extensions)
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* **AVX512F** (AVX-512 Foundation)
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* **AVX512DQ** (AVX-512 Doubleword and Quadword Instructions)
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* **AVX512IFMA** (AVX-512 Integer Fused Multiply-Add Instructions)
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* **AVX512PF** (AVX-512 Prefetch Instructions)
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* **AVX512ER** (AVX-512 Exponential and Reciprocal Instructions)
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* **AVX512CD** (AVX-512 Conflict Detection Instructions)
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* **AVX512BW** (AVX-512 Byte and Word Instructions)
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* **AVX512VL** (AVX-512 Vector Length Extensions)
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* **AVX512VBMI** (AVX-512 Vector Bit Manipulation Instructions)
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* **AVX512VBMI2** (AVX-512 Vector Bit Manipulation Instructions, Version 2)
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* **AVX512VNNI** (AVX-512 Vector Neural Network Instructions)
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* **AVX512VPOPCNTDQ** (AVX-512 Vector Population Count Doubleword and Quadword)
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* **GFNI** (Galois Field New Instructions)
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* **VAES** (Vector AES)
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* **AVX512BITALG** (AVX-512 Bit Algorithms)
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* **VPCLMULQDQ** (Carry-Less Multiplication Quadword)
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* **AVX512BF16** (AVX-512 BFLOAT16 Instructions)
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* **AVX512VP2INTERSECT** (AVX-512 Intersect for D/Q)
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* **MPX** (Intel MPX (Memory Protection Extensions))
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* **ERMS** (Enhanced REP MOVSB/STOSB)
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* **RDTSCP** (RDTSCP Instruction)
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* **CX16** (CMPXCHG16B Instruction)
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* **SGX** (Software Guard Extensions, with activation details)
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* **VMX** (Virtual Machine Extensions)
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## Performance
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* **RDTSCP()** Returns current cycle count. Can be used for benchmarking.
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* **SSE2SLOW** (SSE2 is supported, but usually not faster)
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* **SSE3SLOW** (SSE3 is supported, but usually not faster)
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* **ATOM** (Atom processor, some SSSE3 instructions are slower)
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* **Cache line** (Probable size of a cache line).
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* **L1, L2, L3 Cache size** on newer Intel/AMD CPUs.
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## ARM CPU features
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# ARM FEATURE DETECTION DISABLED!
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See [#52](https://github.com/klauspost/cpuid/issues/52).
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Currently only `arm64` platforms are implemented.
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* **FP** Single-precision and double-precision floating point
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* **ASIMD** Advanced SIMD
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* **EVTSTRM** Generic timer
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* **AES** AES instructions
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* **PMULL** Polynomial Multiply instructions (PMULL/PMULL2)
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* **SHA1** SHA-1 instructions (SHA1C, etc)
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* **SHA2** SHA-2 instructions (SHA256H, etc)
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* **CRC32** CRC32/CRC32C instructions
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* **ATOMICS** Large System Extensions (LSE)
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* **FPHP** Half-precision floating point
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* **ASIMDHP** Advanced SIMD half-precision floating point
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* **ARMCPUID** Some CPU ID registers readable at user-level
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* **ASIMDRDM** Rounding Double Multiply Accumulate/Subtract (SQRDMLAH/SQRDMLSH)
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* **JSCVT** Javascript-style double->int convert (FJCVTZS)
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* **FCMA** Floating point complex number addition and multiplication
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* **LRCPC** Weaker release consistency (LDAPR, etc)
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* **DCPOP** Data cache clean to Point of Persistence (DC CVAP)
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* **SHA3** SHA-3 instructions (EOR3, RAXI, XAR, BCAX)
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* **SM3** SM3 instructions
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* **SM4** SM4 instructions
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* **ASIMDDP** SIMD Dot Product
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* **SHA512** SHA512 instructions
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* **SVE** Scalable Vector Extension
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* **GPA** Generic Pointer Authentication
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## Cpu Vendor/VM
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* **Intel**
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* **AMD**
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* **VIA**
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* **Transmeta**
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* **NSC**
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* **KVM** (Kernel-based Virtual Machine)
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* **MSVM** (Microsoft Hyper-V or Windows Virtual PC)
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* **VMware**
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* **XenHVM**
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* **Bhyve**
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* **Hygon**
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# installing
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```go get github.com/klauspost/cpuid```
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# example
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```Go
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package main
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import (
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"fmt"
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"github.com/klauspost/cpuid"
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)
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func main() {
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// Print basic CPU information:
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fmt.Println("Name:", cpuid.CPU.BrandName)
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fmt.Println("PhysicalCores:", cpuid.CPU.PhysicalCores)
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fmt.Println("ThreadsPerCore:", cpuid.CPU.ThreadsPerCore)
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fmt.Println("LogicalCores:", cpuid.CPU.LogicalCores)
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fmt.Println("Family", cpuid.CPU.Family, "Model:", cpuid.CPU.Model)
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fmt.Println("Features:", cpuid.CPU.Features)
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fmt.Println("Cacheline bytes:", cpuid.CPU.CacheLine)
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fmt.Println("L1 Data Cache:", cpuid.CPU.Cache.L1D, "bytes")
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fmt.Println("L1 Instruction Cache:", cpuid.CPU.Cache.L1D, "bytes")
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fmt.Println("L2 Cache:", cpuid.CPU.Cache.L2, "bytes")
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fmt.Println("L3 Cache:", cpuid.CPU.Cache.L3, "bytes")
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// Test if we have a specific feature:
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if cpuid.CPU.SSE() {
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fmt.Println("We have Streaming SIMD Extensions")
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}
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}
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```
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Sample output:
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```
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>go run main.go
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Name: Intel(R) Core(TM) i5-2540M CPU @ 2.60GHz
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PhysicalCores: 2
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ThreadsPerCore: 2
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LogicalCores: 4
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Family 6 Model: 42
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Features: CMOV,MMX,MMXEXT,SSE,SSE2,SSE3,SSSE3,SSE4.1,SSE4.2,AVX,AESNI,CLMUL
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Cacheline bytes: 64
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We have Streaming SIMD Extensions
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```
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# private package
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In the "private" folder you can find an autogenerated version of the library you can include in your own packages.
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For this purpose all exports are removed, and functions and constants are lowercased.
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This is not a recommended way of using the library, but provided for convenience, if it is difficult for you to use external packages.
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# license
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This code is published under an MIT license. See LICENSE file for more information.
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